Integrated circuits are manufactured with a very high precision process, but their extremely small features still result in a wide range of variability of their runtime characteristics. For example, performance is often measured in terms of maximum achievable clock frequency, and power consumption, often heavily depends on the same parameters of those extremely small features that can ultimately determine performance.
Designers normally handle this variability by assuming at design time that the circuit works under worst-case conditions, i.e. that it delivers its required performance and consumes no more than its maximum power when its process, voltage, temperature and aging conditions are at their worst value. Methods to reduce that pessimism at design time, i.e. statistical static timing analysis, only consider the combinations of those conditions that never, or almost never, occur in practice.
Testing practices may be employed to identify specific integrated circuits that are shown (e.g. via testing) to operate within some band of variability. Of course, such testing techniques generally measure the performance of the critical paths only at testing time, and thus serve only to identify variability in the manufacturing processes, and then only under the specific voltage and environmental conditions present during the testing procedures. However, there is a need to continuously determine the maximum frequency of operation of a semiconductor IC. Such a need applies at post-manufacturing testing time, and/or periodically to estimate its aging, and/or continuously during ongoing operation of the semiconductor IC. Further, there is a need to measure the actual performance of the circuit while ‘in the field’ in order to manage performance and/or power dissipation while the semiconductor IC is in the field under fluctuating voltage and environmental conditions.
These and other reasons motivate the advances as disclosed herein.